Recent advances in solid state technology have produced low cost high density memory chips. For example, a Static Random Access Memory (SRAM) marketed by Mitsubishi Electric Company as part number M5M5256 is capable of storing 256,000 bits in a Very Small Outline Package (VSOP) chip having a 28 pin surface mount design with a molded body only 0.465".times.0.315" and a lead spacing of only 0.0217" between centers. In order to fully benefit from these high density memory chips, high density packaging of the chips on a mounting surface, for example a printed circuit board, must also be provided. In fact, as chip integration becomes more and more dense, the packaging for the chips has become the limiting factor on the ultimate density of the memory module. This is particularly the case with memory chips in which many parallel circuit board connections for power, ground, control, address and data signals are required.
Present day high density packaging techniques typically employ multilayer printed circuit boards having complicated wiring patterns on the outer surfaces thereof and two or more interior layers for bringing signals to the outer surfaces using vias or plated through holes. As the physical dimensions of the chips decrease and the memory density increases, it has become more difficult to connect these chips together in an efficient manner. For example, when the pin spacing is 0.0217" as in the above mentioned Mitsubishi chip, there is no room to run surface wires between the pins for memory interconnection. Rather than running wires between pins, vias leading to intermediate layers must be used. Unfortunately, vias require large board area for drilling and plating, and may create reliability problems. As the chip density increases, the large number of vias limits the overall chip packaging density.
These problems are illustrated by a prior art memory module incorporating an array of the above-mentioned Mitsubishi 256K VSOP SRAM chips. FIG. 1 illustrates the pin configuration for the Mitsubishi 256K VSOP SRAM. To simplify packaging, the SRAM is produced in a "normal lead" and "reverse lead" configuration. In the "normal lead" configuration, the pins are numbered around the package in a counterclockwise manner, starting just to the left of the center line on one of the narrow sides. In a "reverse lead" configuration, the same molded part is used, however the package is turned over when put into the lead forming press. The leads are therefore numbered clockwise, starting to the right of the center line on one narrow side. An indicator (for example a large or small dot) on the chip body distinguishes between normal and reverse lead chips.
FIG. 2 illustrates a prior art technique for connecting a normal and reverse chip of FIG. 1. Due to the mirror image pin configuration of the normal and reverse chips, like pins may be connected together by a plurality of parallel concentric conductors. A separate connection is required only for the "Chip Select" (/CS) pins to permit individual chip selection.
The wiring pattern of FIG. 2 simplifies the connection between two chips, but it has a number of shortcomings for connecting arrays of chips. While this pattern is expandable in the horizontal direction to accommodate additional columns of chips, it cannot readily accommodate more than two rows of chips. The pattern of FIG. 2 may only be expanded in the vertical direction to accommodate three or more rows by providing a via for each conductor to route the wiring to other rows through interior layers. These vias, which are required for three or more rows, severely limit chip packing density. Moreover, even in a two-row array, the large number of concentric conductors under the chips requires very thin conductors to avoid short circuits between adjacent conductors. These thin conductors are difficult to make and may cause reliability problems.